First Workshop on
Programmability Issues for Multi-Core Computers
(MULTIPROG)
Held in conjunction with:
the 3rd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC)
Goteborg, Sweden, January 27, 2008
As computer manufacturers are embarking on the multi-core roadmap, which promises a doubling of the number of processors on a chip every other year, the programming community is faced with a severe dilemma. Until now, software has been developed with a single processor in mind and it needs to be parallelized to take advantage of the new breed of multi-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.
This workshop aims to bring together, and cause fruitful interaction between, researchers interested in programming models and their implementation and in computer architecture with the common interest in advancing our knowledge how to simplify the task of parallelization of software for multi-core platforms. A wide spectrum of issues are central themes for this workshop such as what the future programming models should look like to accelerate software productivity and how it should be implemented at the runtime, the compiler, and the architecture level.
We will prioritize papers reporting on on-going work that address cross-cutting issues and that provide thought-provoking insights into the main themes. A special issue that contains selected papers is planned for the second issue of Transactions on HiPEAC in June 2008. All the papers will be published on the workshop informal proceedings.
Topics of interest
Papers are sought on topics including, but not limited to:
- Multi-core architectures
- Architectural support for compilers/programming models
- Processor (core) architecture
- Memory system architecture
- Performance/power issues
- Programming models for multi-core architectures
- Language extensions
- Run-time systems
- Compiler optimizations and techniques
- Applications for multi-core architectures
- Methodologies
- Benchmarking
Important dates
Submission deadline: Oct 19, 2007 (extended from Oct 5, 2007)
Notification to authors: Nov 23, 2007
Final version of accepted papers: Dec 14, 2007
Paper submission
Submitted papers should use the LNCS format and should be 12 pages maximum. Manuscript preparation guidelines can be found at the LNCS specification web site (go to -> For Authors -> Information for LNCS Authors).
In order to submit your paper go to
this link.
Advanced program
| 09:00-09:10 | Opening remarks |
| 09:10-10:10 | Keynote session: Back to Babel?, Jesus Labarta, BSC and UPC [Abstract] |
| 10:10-10:40 | Coffee break |
| 10:40-12:00 | SESSION 1: Parallelism exploration & multicore systems |
| Autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems | |
| Michael Ott, TU Munchen Tobias Klug, TU Munchen; Josef Weidendorfer, TU Munchen Carsten Trinitis, TU Munchen | |
| Adaptive Concurrency Control for Transactional Memory | |
| Mohammad Ansari, The University of Manchester; Christos Kotselidis, The University of Manchester;Kimberly Jarvis, The University of Manchester; Mikel Lujan, The University of Manchester; Chris Kirkham, The University of Manchester; Ian Watson, The University of Manchester | |
| Thread-Level Speculation for Coarse-Grained Parallelism | |
| Ravi Ramaseshan, North Carolina State University; Frank Mueller, North Carolina State University; Ravi Ramaseshan, NC State University | |
| Improving the Performance of Transactional Memory Systems by Intermediate Checkpoints | |
| M.M. Waliullah and Per Stenstrom, Chalmers University of Technology | |
| 12:00-13:30 | Lunch |
| 13:30-14:50 | SESSION 2: Parallelism in applications |
| Parallel Scalability of H.264 | |
| Cor Meenderinck, Delft University of Technology; Arnaldo Azevedo, Delft University of Technology; Mauricio Alvarez, University of Catalonia (UPC); Ben Juurlink, Delft University of Technology; Alex Ramirez, Barcelona Supercomputing Center | |
| A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs | |
| Olivier Certner, INRIA; Zheng Li, INRIA; Pierre Palatin, INRIA; Olivier Temam, INRIA; Frederic Arzel, Pierre & Marie Curie University; Nathalie Drach, Pierre & Marie Curie University | |
| Detecting the Existence of Coarse-Grain Parallelism in General-Purpose Programs | |
| Sean Rul, Ghent University; Hans Vandierendonck, Ghent University; Koen De Bosschere, Ghent University | |
| Performance Tuning of the Fast Fourier Transform on a Multi-core Architecture | |
| Liping Xue, University of Delaware; Long Chen, University of Delaware; Ziang Hu, University of Delaware; Guang R. Gao, University of Delaware | |
| 14:50-15:20 | Coffee break |
| 15:20-16:40 | SESSION 3: Multicore programming |
| Strict and relaxed sieving for multi-core programming | |
| Anton Lokhmotov, University of Cambridge; Alastair Donaldson, Codeplay Software; Alan Mycroft, University of Cambridge; Colin Riley, Codeplay Software | |
| Safe Reactive Programming: the FunLoft Proposal | |
| Frederic Boussinot, INRIA; Frederic Dabrowski, IRISA | |
| Design of Scalable Dense Linear Algebra Libraries for Multithreaded Architectures: the LU Factorization | |
| Gregorio Quintana-Orti, Universidad Jaume I, 12.071-Castellon; Enrique S. Quintana-Orti, Universidad Jaume; Ernie Chan, The University of Texas at Austin; Robert A. van de Geijn; The University of Texas at Austin,; Field G. Van Zee,The University of Texas at Austin | |
| Hierarchically Tiled Arrays Vs. Intel Threading Building Blocks for Programming Multicore Systems | |
| Diego Andrade, University of A Coruna; James Brodman, University of Illinois at Urbana-Champaign; Basilio B. Fraguela, University of A Coruna; David Padua, University of Illinois at Urbana-Champaign | |
| 16:40-16:50 | Closing |
Organizers
| Eduard Ayguade | Barcelona Supercomputing Center | Spain | eduard[at]ac.upc.edu |
| Roberto Gioiosa | Barcelona Supercomputing Center | Spain | roberto.gioiosa[at]bsc.es |
| Per Stenstrom | Chalmers University of Technology | Sweden | pers[at]chalmers.se |
| Osman Unsal | Barcelona Supercomputing Center | Spain | osman.unsal[at]bsc.es |
Program commitee
| David Bernstein | IBM Research Lab in Haifa | Israel |
| Mats Brorsson | KTH | Sweden |
| Barbara Chapman | University of Houston | USA |
| Marcelo Cintra | University of Edinburgh | U.K. |
| Magnus Ekman | Sun Microsystems | USA |
| Pascal Felber | University of Neuchatel | Switzerland |
| Guang Gao | University of Delaware | USA |
| Roberto Giorgi | University of Siena | Italy |
| Rachid Guerraoui | EPFL | Switzerland |
| Erik Hagersten | Uppsala University | Sweden |
| Tim Harris | Microsoft Research - Cambridge | U.K. |
| Michael Hohmuth | AMD - Dresden | Germany |
| Haoquiang Jin | NASA Ames | USA |
| Stefanos Kaxiras | University of Patras | Greece |
| Ami Marowka | Shenkar College of Engineering and Design | Israel |
| Milo Martin | University of Pennsylvania | USA |
| Avi Mendelson | Intel | USA |
| Dieter an Mey | RWTH, Aachen | Germany |
| Kathy O'Brien | IBM Watson Research | USA |
| Mitsuhisa Sato | University of Tsukuba | Japan |
| Sanjiv Shah | Intel | USA |
| Andre' Seznec | IRISA | France |
| Peng Wu | IBM Watson Research | USA |
Webmaster: roberto.gioiosa[at]bsc.es